View NT6881_42070.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NT6881
USB Keyboard Micro-Controller
Features
n Built-in 6502 8-bit CPU n 3 MHz CPU operation frequency when oscillator is running at 6 MHz n 6K bytes of ROM n 256 bytes of SRAM n One 8-bit programmable base timer with pre-divider circuit n 29 programmable bi-directional I/O pins including two external interrupts n n n n n n n n n 3 LED direct sink pins with internal serial resistors On-chip oscillator (Crystal or Ceramic Resonator) Watch-dog timer reset Built-in power on reset USB interface 3 Endpoints provided Remote Wakeup provided CMOS technology for low power consumption 40-pin DIP package, 42-pad Chip Form and COB
General Description
The NT6881 is a single chip micro-controller for USB keyboard applications. It incorporates a 6502 8-bit CPU core, 6K bytes of mask ROM, and 256 bytes of RAM used as working RAM and stack area. It also includes 29 programmable bi-directional I/O pins with built-in resistors, and one 8-bit pre-loadable base timer. Additionally, it includes a built-in power-on reset, a builtin low voltage reset, an oscillator that requires crystal or ceramic resonator applied, and a watch-dog timer that prevents system standstill.
Pin Configuration
Pad Configuration
V D P V C P G N D G N D O S C I 42 O S C O 41 V C C V C C 38 40 39 37 VDM 5 36 35 P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 6 34 7 33 P25 P24 P23 P22 P21 P20 P17 8 9 10 30 11 29 12 28 13 27 14 16 15 17 18 19 20 21 22 23 24 25 26 P26 LED2 LED1 LED0 P27
GND VCP VDP VDM P30 P31 INT0/P32 INT1/P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OSCI OSCO VDD LED2 LED1 LED0 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12
4
3
2
1
NT6881
NT6881H
32 31
P 0 4
P 0 5
P 0 6
P 0 7
P 1 0
P 1 1
P 1 2
P 1 3
P 1 4
P 1 5
P 1 6
1
V2.6
NT6881
Block Diagram
OSCI Timing Generator OSCO Power Down/Up
Transceiver
VCP VDP VDM
SIE 6502 CPU 6K Bytes Mask ROM Serial Bus Manager 256 Bytes SRAM FIFOs Watch Dog Timer VDD GND RESET Power-On Reset Base Timer I/O PORTs
Interrupt Controller
LED0 LED1 LED2 P00~P07 P10~P17 P20~P27 P30~P34
2
NT6881
Pin and Pad Descriptions
Pin No. 1 2 3 4 5 Pad No. 1,2 3 4 5 6 Designation GND VCP VDP VDM P30 I/O P O I/O I/O I/O Ground USB 3.3V driver USB data plus USB data minus Bi-directional I/O Program output enable 6 7 P31 I/O Bi-directional I/O Program control 7 8 9 10 8 9 10 11 P32/INT0 P33/INT1 P34
RESET
Description
I/O I/O I/O I
Bi-directional I/O shared with INT0 Bi-directional I/O shared with INT1 Bi-directional I/O Internally pulled down resistor Program supply voltage
11 ~ 18
12~19
P00 ~ P07
I/O
Bi-directional I/O Program address buffer
19 ~ 23
20~24
P10 ~ P14
I/O
Bi-directional I/O Program address buffer
24
25
P15
I/O
Bi-directional I/O Program chip enable
25 ~ 26 27 ~ 34
26~27 28~35
P16 ~ P17 P20 ~ P27
I/O I/O
Bi-directional I/O Bi-directional I/O Program data buffer
35
36
LED0
O
LED direct sink Mode selection
36
37
LED1
O
LED direct sink Mode selection
37
38
LED2
O
LED direct sink Mode selection
38 39 40
39,40 41 42
VDD OSCO OSCI
P O I
Power supply (+5V) Crystal oscillator output Crystal oscillator input
3
NT6881
Functional Description
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory range, and interrupt input. Other features are also included. The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for more detailed information.
7 Accumulator A 7 Index Register Y 7 Index Register X 15 Program Counter PCH PCL 7 7 Stack Pointer SP 7 N V B D I Z
0
0
0
8
0 0
0 C Status Register P
Carry Zero IRQ Disable Decimal Mode BRK Command Overflow Negative
1 = TRUE 1 = Result ZERO 1 = DISABLE 1 = TRUE 1 = BRK 1 = TRUE 1 = NEG
Figure 1.1. 6502 CPU Registers and Status Flags
4
NT6881
2.Instruction Set List Instruction Code ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR Meaning Add with carry Logical AND Shift left one bit Branch if carry clear Branch if carry set Branch if equal to zero Bit test Branch if minus Branch if not equal to zero Branch if plus Break Branch if overflow clear Branch if overflow set Clear carry Clear decimal mode Clear interrupt disable bit Clear overflow Compare accumulator to memory Compare with index register X Compare with index register Y Decrement memory by one Decrement index X by one Decrement index Y by one Logical exclusive-OR Increment memory by one Increment index X by one Increment index Y by one Jump to new location Jump to subroutine Operation A + M + C / AAC AEM / A C o M7EEE 0 o 0 M Branch on Cx0 Branch on Cx1 Branch on Zx1 AEMAM7 / NAM6 / V Branch on Nx1 Branch on Zx0 Branch on Nx0 Forced interrupt PC + 2o PCo Branch on Vx0 Branch on Vx1 0 / C 0 / D 0 / I 0 / V A M X M Y M M 1 / M X 1 / X Y 1 / Y A o M/A M + 1 / M X + 1 / X Y + 1 / Y (PC + 1) / PCLA(PC + 2) / PCH PC + 2oA(PC + 1) / PCLA(PC + 2) / PCH
5
NT6881
Instruction Set List (contiuned) Instruction Code LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA Meaning Load accumulator with memory Load index register X with memory Load index register Y with memory Shift right one bit No operation Logical OR Push accumulator on stack Push status register on stack Pull accumulator from stack Pull status register from stack Rotate left through carry Rotate right through carry Return from interrupt Return from subroutine Subtract with borrow Set carry Set decimal mode Set interrupt disable status Store accumulator in memory Store index register X in memory Store index register Y in memory Transfer accumulator to index X Transfer accumulator to index Y Transfer stack pointer to index X Transfer index X to accumulator Transfer index X to stack pointer Transfer index Y to accumulator M / A M / X M / Y 0 / M7EEE 0 / C M No operation (2 cycles) A + M / A A o P o A o P o C o M7EEE 0 o C M C / M7EEE 0 / C M P oAPC o PC oAPC+1 / PC A M C / AAC 1 / C 1 / D 1 / I A / M X / M Y / M A / X A / Y S / X X / A X / S Y / A Operation
* For more detailed specifications, please refer to 6502 programming data book.
6
NT6881
3. Mask ROM: 6K X 8 bits
The built-in mask ROM program code, executed by the 6502 CPU, has a capacity of 6K X 8-bit and is addressed from E800H to FFFFH. 4. SRAM: 256 X 8 bits The built-in SRAM is used for general purpose data memory and for stack area. SRAM is addressed from 0080H to 017FH. Because the 6502 default stack pointer is 01FFH, the stack area will map $01FF-$0180 to $00FF-$0080, thus the programmer can set "S" register to 7FH when starting program, allowing stack point is 017FH. as; LDX TXS #$7F
$0000 $001F
System Registers
Unused $0080 $00FF $0100 $017F
RAM
RAM stack pointer
Unused
$E800 ROM $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF NMI-L NMI-H RST-L RST-H IRQ-L IRQ-H IRQ Vector RESET Vector NMI Vector
7
NT6881
5. System Reserved Registers
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Register IRQFUNC IRQCLRF IE_FUNC IRQUSB IRQCLRU IE_USB BT TCON TMOD PORT0 PORT1 PORT2 PORT3 LED CLRWDT MODE_FG Reset 00H 00H 00H 00H 00H 00H 00H 01H 00H FFH FFH FFH 1FH 07H 00H 02H Bit 7 SUSP CSUSP ESUSP BT7 P07 P17 P27 0 Bit 6 STUP CSTUP ESTUP BT6 P06 P16 P26 1 Bit 5 BT5 P05 P15 P25 0 Bit 4 BT4 P04 P14 P24 P34 1 Bit 3 KBD CKBD EKBD IN2 CIN2 EIN2 BT3 P03 P13 P23 P33 0 Bit 2 INT1 CINT1 EINT1 IN1 CIN1 EIN1 BT2 TM2 P02 P12 P22 P32 LED2 1 Bit 1 INT0 CINT0 EINT0 OT0 COT0 EOT0 BT1 TM1 P01 P11 P21 P31 LED1 0 POF Bit 0 TMR CTMR ETMR IN0 CIN0 EIN0 BT0 R/W R W R/W R W R/W W W R/W R/W R/W R/W R/W W W R/W
ENBT
TM0 P00 P10 P20 P30 LED0 1 SUSF
: no effect
6. Power-on Reset Built-in power-on reset circuit can generate a minimum of 5ms pulse to reset the entire chip. User also can use an external RESET pin to reset the entire chip.
7. Timing Generator This block generates the system timing and control signals supplied to CPU and on-chip peripherals. The crystal oscillator generates a 6MHz system clock. It only generates 3MHz clock for CPU.
8
NT6881
8. Base Timer (BT)
The Base Timer is an 8 -bit counter with a programmable clock source selection. The BT can be enabled/dis abled by the CPU. After reset, the BT is disabled and cleared. The BT can be preset by writing preset value to BT7 ~ BT0 of the BT register at any time. When the BT is enabled, the BT starts counting from the preset value. When the value reaches FFH, it generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the BT will wrap around and begin counting at 00H. The BT can be enabled by writing a "0" to "ENBT " bit in the TCON (Timer Control) register. The ENBT signal is level trigger. The input clock source of BT is controlled by the TMOD register. The following table shows 8 ranges of BT.
TM2 0 0 0 0 1 1 1 1
TM1 0 0 1 1 0 0 1 1
TM0 0 1 0 1 0 1 0 1
Pre-scalar Ratio System Clock/2 3 System Clock/2 4 System Clock/2 5 System Clock/2 6 System Clock/2 7 System Clock/2 8 System Clock/2 9 System Clock/2 10
Min. Count 1.33 s 2.66 s 5.32 s 10.64 s 21.28 s 42.56 s 85.12 s 170.24 s
Max. Count 341.33 s 682.66 s 1.36 ms 2.72 ms 5.44 ms 10.89 ms 21.79 ms 43.58 ms
For counting accuracy, please set the TMOD register first, then preset the BT register, and enable base timer finally. (TM2, TM1, TM0) = (1, 1, 1) is reserved for USB driver use.
9
NT6881
9. Interrupt Controller
There are 10 interrupt sources: Timer, INT0, INT1, KBD, SUSP, IN0, IN1, IN2, OT0 and STUP. 9.1. Timer Interrupt When the BASE TIMER overflows, it will set the TMR flag. If the interrupt is enabled by writing "1" to the bit 0 in IE_FUNC ($0002H), then it will interrupt 6502 CPU. The TMR flag can be read by software. Once set by an interrupt source, it can read from bit0 in IRQFUNC ($0000H) and remains high unless cleared by writing "1" to the bit 0 in IRQCLRF ($0001H). All of register's data are cleared to "0" at initialization by the system reset. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, thus the TMR flag must be cleared by software. 9.2. INT0 Interrupt As soon as INT0 pin detects a falling edge trigger, NT6881 sets the INT0 flag ($0000H, bit1). After that, the 6502 CPU is interrupted if this interrupt has already been enabled already by writing "1" to EINT0 ($0002H, bit1). If EINT0 flag is cleared, 6502 CPU can't be INT0 interrupted even if the INT0 flag is set. INT0 flag can only be set by hardware and can not be set or cleared directly by the software except for writing "1" to CINT0 ($0001H, bit1) flag to clear INT0 flag. When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine so the INT0 flag must be cleared by software.
9.3. INT1 Interrupt As soon as INT1 pin detects a falling edge trigger, NT6881 sets the INT1 flag ($0000H, bit2). Then the 6502 CPU is interrupted if this interrupt has already been enabled already by writing "1" to EINT0 ($0002H, bit2). If EINT1 flag is cleared, 6502 CPU can't be INT1 interrupted even if the INT1 flag is set. INT1 flag can only be set by hardware and can not be set or cleared directly by the software except for writing "1" to CINT1 ($0001H, bit2) flag to clear INT1 flag. When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine so the INT1 flag must be cleared by software. 9.4. KBD Interrupt This interrupt will set the KBD flag ($0000H, bit3) every 4ms(HID 1.00 version) to indicate that keyboard scan data is ready to send for endpoint1. And then 6502 CPU is interrupted if this interrupt has been enabled already by writing "1" to EKBD ($0002H, bit3). If the EKBD flag is cleared, 6502 CPU can't be KBD interrupted even if KBD flag is set. The KBD flag can only be set by the hardware and can not be set or cleared directly by firmware except for writing "1" to CKBD ($0001H, bit 3) flag to clear KBD flag. When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the KBD flag must be cleared by firmware.
9.5. IN0 Token Interrupt When an IN TOKEN for endpoint 0 is done, it will set the IN0 flag. If this interrupt is enabled by writing "1" to EIN0 ($0005H, bit0), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN0 flag must be cleared by the software.
9.6. OT0 (OUT 0) Token Interrupt When an OUT TOKEN for endpoint 0 is done, it will set the OT0 flag. If this interrupt is enabled by writing "1" to EOT0 ($0005H, bit1), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the OT0 flag must be cleared by the software.
10
NT6881
9.7. IN1 Token Interrupt When an IN TOKEN for endpoint 1 is done, it will set the IN1 flag. If this interrupt is enabled by writing "1" to EIN1 ($0005H, bit2), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN1 flag must be cleared by software.
9.8. IN2 Token Interrupt When an IN TOKEN for endpoint 2 is done, it will set the IN2 flag. If this interrupt is enabled by writing "1" to EIN2 ($0005H, bit3), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN2 flag must be cleared by the software.
9.9. STUP (SETUP) Token Interrupt When a SETUP TOKEN for endpoint 0 is done, it will set the STUP flag. If this interrupt is enabled by writing "1" to ESTUP ($0005H, bit6), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the STUP flag must be cleared by the software.
9.10. SUSP Interrupt When USB SIE detects a suspend signal, it sets the SUSP flag. Then 6502 CPU is interrupted if the interrupt has been enabled already by writing "1" to ESUSP ($0005H, bit7). If ESUSP flag is cleared, 6502 CPU can't be SUSP interrupted even if SUSP flag is set. SUSP flag can be set by H/W only and can't be set/cleared directly by S/W except for writing "1" to CSUSP ($0004H, bit 7) flag to clear SUSP flag. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the SUSP flag must be cleared by software.
10. I/O PORTs
The NT6881 has 32 pins dedicated to input and output. These pins are grouped into 5 ports, as follows: PORT0 (P00~P07) PORT0 is an 8-bit bi-directional CMOS I/O port that is internally pulled high by PMOS. Each pin of PORT0 can be bit programmed as an input or output port under software control. When programmed as output, data is latch to the port data register and output to the pin. PORT0 pins with "1" written to them are pulled high by the internal PMOS pull-ups, and can be used as inputs in that state then these input signals can be read. The port will output high after reset. PORT1 (P10~P17): Functions the same as PORT0. PORT2 (P20~P27): Functions the same as PORT0. PORT3 (P30~P34): Functions the same as PORT0. Except for P33/P32 is shared with INT1/INT0 pin. It is also a Schmitt Trigger input with an interrupt source of falling edge sensitive. LED: There are three LED direct sink pins which require no external serial resistors. The address is mapped to $000DH.
11
NT6881
11. Watch-Dog Timer (WDT)
The NT6881 has a watch-dog timer reset function that protects programs against system standstill. The clock of the WDT is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when operation frequency is 6MHz. The timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause system reset. (This cannot be disabled by software) Before watch-dog reset occurred, the software mus t clear watch-dog register by writing #55H to CLRWDT ($000EH) register. For example: LDA STA #$55H $000E
12. Power Control
The power off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is set by hardware when an external power VCC arises to its normal operating level, and must be cleared by software in the cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset. Address $000FH Register MODE_FG Reset 02H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 POF Bit 0 SUSF R/W R/W
13. Universal Serial Bus Interface
Please refer to UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9.
14. Suspend and Resume
Suspend: When SIE receives suspend signal, NT6881 generates SUSP interrupt request. In the SUSP interrupt service routine, the software must carry out following steps: 1) 2) 3) 4) 5) 6) Clear SUSP IRQ flag, Store all the port status, Force return lines (PORT2) pull-high, Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low, Turn off LED output, Clear watch-dog register.
After the above action has been completed, the software must then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to #AAH in order to enter the SUSPEND mode. Finally, oscillator stops in order to save power. Resume: When NT6881 receives a RESUME signal, the chip will resume and the firmware initializes itself. The initialization process includes, checking the status of the POF bit in the MODE_FG register, whereas if the POF bit equals "1", the firmware will enter into a cold reset procedure and clears the POF bit. If the POF bit equals "0" , the firmware will enter into a warm reset procedure. If indeed a warm reset begins, the firmware checks the SUSF bit in MO DE_FG. Regarding the SUSF bit, if it equals "1", the firmware enters into the RESUME procedure and then clears the SUSF bit, however if SUSF equals "0", then the firmware enters into a Watchdog Reset procedure. When any keyboard key is struck and the Remote_Wake_Up bit equals "1", a RESUME signal will be sent to the host, and the above procedure will repeat themselves.
12
NT6881
15. Reset Source Summary
These are 5 reset sources in NT6881 as shown below. No. 1 2 3 4 5 Type Cold Cold Cold Warm-1 Warm-2 Function External Pin ( RESET ) Power-on Reset USB Reset Signaling Resume Reset Watch-dog Reset Description Applied Externally Reset after Power-on 10 ms Reset Period USB Reset Period Reset every 0.15S (OSC = 6MHz)
NT6881 can also be reset e xternally through the RESET pin. A reset is initialed when the signal at the RESET pin is held Low for at least 10 system clocks. When RESET signal goes high, the NT6881 begins to work. The following shows the definition of RESET input low pulse width.
VDD
VDD
20%VDD Trstb
20%VDD
16. PS/2 Mouse Application
A PS/2 mouse interface is implemented in P32 (CLK), P33 (DATA) and P34 (Power Control). The timing diagrams are described as follows.
1st CLK T1 T3 T2 T4 T1A T5 2nd CLK 10th CLK 11th CLK
CLK
DATA
Start Bit
Bit 0
Parity Bit
Stop Bit
Auxiliary Device Sending Data Timings
Timing T1 T1A T2 T3 T4 T5 Description Time from DATA transaction to falling edge of CLK 1 Time from DATA transaction to falling edge of CLK 2-11 Time from rising edge of CLK to DATA transaction Duration of CLK inactive (LOW) Duration of CLK active (HIGH) Time to Auxiliary Device inhibit after clock 11 to ensure the Auxiliary Device does not start another transmission MIN/MAX 5/25u s 5/25u s 5/T4-5u s 30/50u s 30-50u s >0/50u s
13
NT6881
CLK
I/O Inhibit 1st CLK T6 T8 T7 2nd CLK 9th CLK 10th CLK 11th CLK
T9
T10
DATA
Start Bit
Bit 0
Parity Bit
Stop Bit
Line Control Bit
Auxiliary Device Receiving Data Timings
Timing T6 T7 T8 T9 T10 Description Duration of CLK interface (LOW) Duration of CLK active (HIGH) Time from inactive to active CLK transition, used to time when the Auxiliary Device samples DATA Time from falling edge of line control bit to falling edge of clock 11 CLK Time from rising edge of clock 11 to rising edge of line control bit MIN/MAX 30/50u s 30/50u s 5/25u s 5u s/ 5/25 u s
14
NT6881
Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . -0.3V to +7.0V Input/Output Voltage . . . . . GND - 0.2V to V + 0.2V DD Operating Ambient Temperature . . . . . . . 0 C to 70 C Storage Temperature . . . . . . . . . . . -55 C to +125 C Operating Voltage (VDD) . . . . . . . . . . . +4.4V to +5.25V
*Comments
Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25C, Fosc = 6MHz, unless otherwise noted)
Symbol VDD IOP ISP VIH VIL VOH VOL1 VOL2 ILED Parameters Operating Voltage Operating Current Suspend Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage (P0/P1/P2) Output Low Voltage (P3) LED Sink Current 6 10 2.4 0.4 0.4 14 2 0.8 Min. 4.4 Typ. 5 Max. 5.25 20 150 Unit V mA A V V V V V mA IOH = -100A IOL1 = 4mA IOL2 = 5mA VOL = 3.2V No load Note 1 Conditions
Note 1: The test condition of ISP is when both of 2 things occur, 1) an oscillation stop and 2) no application circuit is applied. When an application circuit is applied in the keyboard, and the PC is suspended, the suspend current of the keyboard must be less than 500A.
AC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25C, Fosc = 6MHz, unless otherwise noted)
Symbol FOSC TRSTB TPOR Parameters Oscillator Frequency
RESET Input Low Pulse Width
Min. 5.97 1.67 5
Typ. 6
Max. 6.03
Unit MHz s
Conditions OSC within +/- 0.5% 10 system clocks
Power On Reset Time
30
ms
USB DC/AC SPECIFICATIONS
Please refer to UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7.
15
NT6881
Application Circuit 1 (Simple Keyboard with PS/2 Mouse)
V CC
PS/2 Mouse CLK PS/2 Mouse DATA PS/2 Mouse Power Control
P32 P33 P34
Vcc
10F GND 0.1 F
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31
LED0
Scroll Lock Num Lock
LED1
LED2
NT6881
RESET
Caps Lock
*1
4.7KO OSCI
*1 : RESET can be direct connect to VCC if the external reset is not used for module test.
OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM
6Mhz Crystal D+ To USB Cable D1.5KO
VCP 4.7F
P20 E R U I O + (Num) 9 PgUp 8 7 Home
P21 F3 T Y } ] F7 K107 6 5 (Num) 4 L-Shift
P22 D F J K L Enter (Num) 3 PgDn 2 1 End R-Shift | \(K29) : ; 000 00
P23 F4 G H F6
P24 C V M < , > .
P25 K133 B N K56 APP
P26 F2 % 5 ^ 6 + = F8 Home
P27 # 3 $ 4 & 7 * 8 ( 9 End Page Down Kor_R Kor_L P10 P11 P00 P01 P02 P03 P04
. Del 0 Ins Space
* (Num) / (Num) Num Lock
(Num)
Page Up Insert Delete
P05 P06 P07
K14 P Scroll Lock Pause
Back Space { [
F11 " ' L-Alt
Enter | \(K42)
F12 ? / R-Alt
F9 _ -
F10 ) 0 Print Screen P12 P13 P14 P15 P16
R-Ctrl
L-Ctrl
F5
L-WIN Kor_L Q W
TAB
R-Win A S Esc K45 Z X K131 K132 ~ F1
Kor_R ! 1 @ 2 P17 P30 P31
Caps Lock
Notice: "Return Key" must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
16
NT6881
Application Circuit 2 (Windows 2000 Compatible Keyboard)
VCC
Vcc
1 0F P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 GND 0.1 F
LED0
Scroll Lock Num Lock
LED1
LED2
NT6881
RESET
Caps Lock
4 . 7 KO OSCI
*1
* 1: RESETB can be direct connect to VCC if the external reset is not used for module test.
OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM
6Mhz Crystal D+ To USB Cable D1.5KO
VCP 4.7F
P20 E R U I O + (Num) 9 PgUp 8 7 Home Wake Up K14 P Scroll Lock Pause VolumeKor_L Q W Treble-
P21 F3 T Y } ] F7 K107 6 5 (Num) 4 L-Shift Back Space { [ BassPower Down L-WIN
WWW Forward TAB
P22 D F J K L Enter (Num) 3 PgDn 2 1 End
P23 F4 G H F6 Bass+
P24 C V M < , > . Scan Next * (Num) / (Num) Num Lock
P25 K133 B N K56 APP
P26 F2 % 5 ^ 6 + = F8 Home
P27 # 3 $ 4 & 7 * 8 ( 9 End Page Down Sleep Power Down Volume+
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11
. Del 0 Ins Space
Scan
(Num)
Page Up Insert Delete
R-Shift Previous Stop | \(K29) : ; 000 00 Email F11 " ' L-Alt . Sleep Enter | \(K42) Euro Key R-Ctrl
Play/ Pause F12 ? / R-Alt Wake Up
Mute F9 _ -
F10 P12 P13 P14 P15
) 0 Print Treble+ Screen L-Ctrl Bass Boost F5
WWW Backward
W W W WWW Search H o m e WWW WWW R-Win Stop Refresh A S Esc K45 Z X
P16 P17 P30 P31 P32
WWW Favorite
Kor_R ~ F1 ! 1 @ 2
K131 K132
Caps Lock Media Select
My Calculator Computer
Notice: "Return Key" must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
17
NT6881
Application Circuit 3 (Mini Keyboard)
VCC
Vcc
1 0F P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 GND 0.1 F
LED0
Scroll Lock Num Lock
LED1
LED2
NT6881
RESET
Caps Lock
4 . 7 KO OSCI
*1
* 1: RESETB can be direct connect to VCC if the external reset is not used for module test.
OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM
6Mhz Crystal D+ To USB Cable D1.5KO
VCP 4.7F
P20 E R U *4 I *5(Num) O *6 + (Num) 9 PgUp 8 7 Home Wake Up K14
P21 F3
*FN_K3
P22 D F
P23 F4
*FN_K4
P24 C V M *0 Ins < , >. *. Del
P25 K133 B N K56 APP
P26 F2
*FN_K2
P27 # 3 $ 4 &7 *7 Home *8 *8 ( 9
T Y
G
J H *1 End F6 } K *FN_K6 ] *2 F7 L *FN_K7 *3 PgDn Bass+ K107 6 5 (Num) 4 L-Shift
% 5 ^ 6 + = F8
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32
*FN_K8 *9 PgUp
Back Space P { * -(Num) [
Scroll Lock *Num Lock
BassPower Down L-WIN
WWW Forward TAB
Pause
*FN_K14
VolumeKor_L Q W Treble-
Caps Lock Media Select
Enter Scan Home (Num) *FN_K21 Next *FN_K22 *FN_K16 . 3 Page Up * PgDn Del (Num) (Num) *FN_K17 2 0 / Insert (Num) *FN_K24 *FN_K15 Ins Delete 1 Num Space End Lock *FN_K23 *FN_K18 Scan Play/ R-Shift Previous Stop Mute Pause F12 F9 | F11 Enter *FN_K12 *FN_K9 \(K29) *FN_K11 _ :; | ?/ " * +(Num) \(K42) * /(Num) ' Euro L-Alt R-Alt 000 Treble+ Key . Wake Sleep L-Ctrl 00 R-Ctrl Up W W W WWW Bass Email Search H o m e Boost WWW WWW WWW FN R-Win Stop Refresh Favorite ~ Z Esc K131 A F1 S X K132 *FN_K1 K45
My Calculator Computer
End
*FN_K19 Page Down *FN_K20
Sleep Power Down Volume+ F10
*FN_K10
)0 * *(Num)
Print Screen
*FN_K13
F5
*FN_K5
WWW Backward
Kor_R ! 1 @ 2
Notice: "Return Key" must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work. *: For FN key model usage
18
NT6881
FN Key Model Usage for Keypad FN+Scroll Lock FN+& FN+U FN+J FN+M 7 Num Lock 7 Home 4 1 End 0 Ins FN+* FN+I FN+K 8 8 5(Num) 2 FN + ( FN+O FN+L FN+> . 9 9 PgUp 6 3 PgDn . Del FN+) FN+P FN+: FN+? ; / 0 *(Num) -(Num) +(Num) /(Num)
FN Key Model Usage for Consumer Keys FN_K1 FN_K3 FN_K5 FN_K7 FN_K9 FN_K11 FN_K13 FN_K15 FN_K17 FN_K19 FN_K21 FN_K23 FN+F1 FN+F3 FN+F5 FN+F7 FN+F9 FN+F11 FN+Print Screen FN+Insert FN+Page Up FN+End FN+ FN+ WWW Backward WWW Stop WWW Search WWW Home My Computer Media Select Bass Boost Volume+ Treble+ BassStop Play/Pause FN_K2 FN_K4 FN_K6 FN_K8 FN_K10 FN_K12 FN_K14 FN_K16 FN_K18 FN_K20 FN_K22 FN_K24 FN+F2 FN+F4 FN+F6 FN+F8 FN+F10 FN+F12 FN+Pause FN+Home FN+Delete FN+Page Down FN+ FN+ WWW Forward WWW Refresh WWW Favorite Email Calculator Mute Sleep Bass+ VolumeTrebleScan Previous Track Scan Next Track
19
NT6881
Bonding Diagram
V D P V C P G N D G N D O S C I 42 4 3 2 1 O S C O 41 40 39 37 VDM 5 36 LED1 LED0 P27 P26 P25 P24 P23 P22 P21 P20 P17 2082.8 V C C V C C 38 LED2
P30 P31 P32 P33 P34 RESET P00 P01 P02 P03
6 7
NT6881H
Y
35 34 33 32
8 9 (0, 0) 10 11 29 12 28 13 27 14 16 15 17 18 19 20 21 22 23 24 25 26 X 30 31
P 0 4
P 0 5
P 0 6
P 0 7
P 1 0
P 1 1
P 1 2
P 1 3
P 1 4
P 1 5
P 1 6
2235.2 m
Substrate connect to GND Unit: m Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Designation GND GND VCP VDP VDM P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 X -28.90 -163.90 -424.10 -841.85 -924.35 -979.05 -980.35 -980.40 -980.40 -980.50 -980.70 -980.30 -980.30 -980.40 -980.40 -601.05 -350.25 -218.25 52.15 182.15 312.15 Y 806.90 806.95 819.55 828.05 549.95 275.10 140.70 10.65 -119.30 -249.30 -380.20 -509.30 -639.25 -769.30 -899.30 -859.30 -859.30 -859.30 -901.40 -901.40 -901.40 Pad No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Designation P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 LED2 VCC VCC OSCO OSCI X 442.15 572.15 702.15 832.15 962.15 980.50 980.45 980.35 980.35 980.40 980.15 980.45 980.40 980.35 980.40 980.40 980.40 685.45 512.75 288.75 158.75 Y -901.40 -901.40 -901.40 -901.40 -901.40 -561.55 -426.75 -292.35 -162.50 -32.40 97.60 227.65 357.55 487.75 628.70 754.80 888.75 793.80 793.80 883.80 883.80
20
NT6881
Ordering Information
Part No. NT6881H NT6881 Packages CHIP FORM 40L DIP
Standard code functional descriptions
Code Number NT6881-D01012 Name Simple Keyboard with PS/2 Mouse Windows 2000 Compatible Keyboard Reference application circuit Application circuit 1 Functional Description 1. PS/2 mouse port 2. '000' and '00' keys Application circuit 2 1. ACPI keys 2. '000', '00' and Euro keys 3. Consumer keys (Windows 2000) NT6881-D01014 Mini Keyboard Application circuit 3 1. ACPI keys 2. ` 000' ` and Euro keys , 00' 3. Consumer keys (Windows 2000) 4. FN key and 40 Translated keys
NT6881-D01013
21
NT6881
Package Information P-DIP 40L Outline Dimensions
unit: inches/mm
D 40 21
E1
1 S
20 E C
A2
A
A1
Base Plane
Seating Plane B B1 e1 a eA
L
Symbol A A1 A2 B B1 C D E E1 e1 L \ eA S
Dimensions in inches Dimensions in mm 0.210 Max. 5.33 Max. 0.010 Min. 0.25 Min. 0.1550.010 3.940.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.050 +0.004 1.27 +0.10 -0.002 -0.05 0.010 +0.004 0.25 +0.10 -0.002 -0.05 2.055 Typ. (2.075 Max.) 52.20 Typ. (52.71 Max.) 0.6000.010 15.240.25 0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.) 0.1000.010 2.540.25 0.1300.010 3.300.25 0~ 15 0~ 15 0.6550.035 0.093 Max. 16.640.89 2.36 Max.
Note: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
22
NT6881
Product Spec. Change Notice NT6881 Specification Revision History Version 2.7 Content FN Key Model Usage for Consumer Keys modified - FN_K22 and FN_K24 (Page 19) Volume Knob Application deleted (Page 13) PS/2 Mouse Application added (Page 13 and 14) Application circuit 2 and 3 modified (Page 17 and 18) FN key usage added (Page 19) Standard code functional descriptions modified (Page 21) Application circuits modified (Page 15, 16 and 17) Standard code functional description added (Page19) Original Data Oct. 2002
2.6
Sep. 2002
2.5
July 2002
1.0
Nov. 1998
23

▲Up To Search▲

Price & Availability of NT6881

	To Download NT6881 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .